Job Description:
1. At least 4 years of experience with pre-silicon DV (Design Verification)
2. Must have hands-on experience with writing code using System Verilog and UVM over the past 2 years
3. Must be a quick learner, independent and communicate well.
4. Knowledge and hands on experience with Verilog, System Verilog, UVM, debugging waveforms
5. Must be proficient with :
◦ building a testbench for a medium complexity block using System Verilog and UVM
◦ Writing random tests, directed tests, error tests & performance tests for a block of medium complexity using System Verilog and UVM.
◦ Debugging tests with design engineers to deliver functionally correct design blocks
◦ OOPS, randomization, constraints, interfaces
◦ writing & analyzing functional coverage, assertions
◦ Generating and analyzing code coverage & writing waivers